HPCAT NEWS

Congrats to Jiaqi on her accepted TPDS paper.

Jiaqi Yang, Hao Zheng, and Ahmed Louri, “Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration,” in IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 2, pp. 349-361, February 2024.

Congrats to Dr. Li on his accepted TPDS paper.

Yuan Li, Ahmed Louri, and Avinash Karanth, "A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration," in IEEE Transactions on Parallel and Distributed Systems (TPDS), 2023.

HPCAT was featured on the GW Engineering Website.

HPCAT work on designing next-generation computing architectures was featured on the GW Engineering Website. [Link]

Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, and Hao Zheng, "Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration," to appear in IEEE International Conference on Computer Design (ICCD), Washington, DC, November 6-8, 2023.

Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, and Hao Zheng, "ARIES: Accelerating Distributed Training in Chiplet-based Systems via Flexible Interconnects," to appear in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, October 29-November 2, 2023.

Prof. Louri has one paper accepted to ACM/IEEE International Symposium on Computer Architecture (ISCA).

Kyle Shiflett, Avinash Karanth, Razvan Bunescu, and Ahmed Louri, "Flumen: Dynamic Processing in the Photonic Interconnect," to appear in Proceedings of 50th ACM/IEEE International Symposium on Computer Architecture (ISCA), Orlando, FL, June 17-21, 2023.

Prof. Louri and his student Dr. Hao Zheng receive a U.S. patent.

Hao Zheng and Ahmed Louri. 
"EZ-Pass: An Energy Performance-Efficient Power-Gating Router Architecture for Scalable On-Chip Interconnect Architecture." Patent No. US 11,502,934 B2

Prof. Louri and his students, Dr. Hao Zheng and Dr. Ke Wang receive a U.S. patent.

Ahmed Louri, Hao Zheng, and Ke Wang. 
"Interconnection Network with Adaptable Router Lines for Chiplet-Based Manycore Architecture." Patent No. US 11,489,788 B2

Congrats to Yuechen on his accepted NAS paper!

Congrats to our PhD student Yuechen on his accepted NAS 2022 paper: Yuechen Chen, Ahmed Louri, Shanshan Liu, and Fabrizio Lombardi, "Approximate Network-on-Chips with Application to Image Classification," which is to appear in Proceedings of the IEEE International Conference on Networking, Architecture, and Storage, Philadelphia, PA, October 3-4, 2022.

Congrats to Jiaqi and Dr. Zheng on their accepted GLSVLSI paper!

Congrats to our PhD student Jiaqi and Dr. Hao Zheng on their accepted GLSVLSI 2022 paper: Jiaqi Yang, Hao Zheng, and Ahmed Louri, "Adapt-Flow: A Flexible DNN Accelerator Design for Heterogeneous Dataflow," which is to appear in Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), Irvine, CA, June 6-8, 2022.

Congrats to Yuan on his accepted HPCA paper!

Congrats to our PhD student Yuan Li on his accepted HPCA 2022 paper: Yuan Li, Ahmed Louri, and Avinash Karanth, "SPACX: Silicon Photonic-based Scalable Chiplet Accelerator for DNN Inference" which is to appear in Proceedings of the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, South Korea, February 12-16, 2022.

Prof. Ahmed Louri received a National Science Foundation award for the project “Holistic Design of High-performance and Energy-efficient Accelerators for Graph Neural Networks”.

Prof. Ahmed Louri has been awarded a three-year, $500,000 National Science Foundation grant for the project “Holistic Design of High-performance and Energy-efficient Accelerators for Graph Neural Networks.” Graph Neural Networks (GNNs) have recently emerged as one of the most powerful techniques for next generation learning systems, and they are gaining attention in many high-impact domains such as graph mining (graph machine, graph clustering), biology (drug discovery, disease classification), traffic networks (traffic prediction), recommendation systems, autonomous systems, and security, among many others. In this project, Dr. Louri will develop a holistic design framework spanning architecture study, Network-on-Chip (NoC) design, machine learning algorithms development, and algorithm-architecture co-optimization, with the aim of designing energy-efficient and high-performance scalable accelerator architectures for GNNs. Such a framework will have far-reaching implications for future machine learning architectures and applications. The project will also play a major role in education by integrating discovery with teaching and training.

Prof. Louri Receives The George Washington University 2021 Office of the Vice-President for Research, Distinguished Researcher Award!

Congratulations to Prof. Ahmed Louri, who was selected to receive the GWU 2021 Office of the Vice-President for Research (OVPR), Distinguished Researcher Award. The OVPR Distinguished Researcher Award recognizes GWU faculty members who have made significant contributions in research and scholarship to the university and society. The award is given annually to just one GWU faculty member.

Congrats to Dr. Li on his accepted TSUSC paper!

Congrats to Dr. Jiajun Li on his accepted paper: Jiajun Li and Ahmed Louri, "AdaPrune: An Accelerator-aware Pruning Technique for Sustainable CNN Accelerators", which is accepted to publish in IEEE Transactions on Sustainable Computing, DOI: 10.1109/TSUSC.2021.3060690, 2021.

Yuechen presented his paper in CODES+ISSS! 

Dr. Ahmed Louri (ECE) and his Ph.D. students, Yuchen, presented the paper “Learning-based Quality Management for Approximate Communication in Network-on-Chips” at International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), held September 20-25, 2020.

Congrats to Cory and Hao on their accepted IEEE Micro paper!” 

Dr. Ahmed Louri (ECE) and his Ph.D. students, Ke Wang and Hao Zheng, have published a refereed journal paper: K. Wang, H. Zheng, and A. Louri. “TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-On-Chip Architecture,” IEEE Micro: Special Issue on Machine Learning for Systems, DOI: 10.1109/MM.2020.3003576, June 2020. The work exploits the use of machine learning to detect hardware Trojans in Network-on-Chip and presents a high-performance and energy-efficient design for threat mitigation.

Congrats to Cory on his accepted TPDS paper!” 

Dr. Ahmed Louri (ECE) and his Ph.D. student Ke Waing have published the following paper: K. Wang and A. Louri. “CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning,” IEEE Transactions on Parallel and Distributed Systems. DOI: 10.1109/TPDS.2020.2986297. The work exploits the use of reinforcement learning and presents a Network-on-Chip design that simultaneously reduces network latency, improves energy-efficiency, and tolerates transient errors and permanent faults. This research is funded by a grant from the National Science Foundation.

Congrats to Yuechen Chen on his accepted TPDS paper!” 

Dr. Ahmed Louri (ECE) and his Ph.D. student Yuechen Chen have published the following paper: Y. Chen and A. Louri, “An Approximate Communication Framework for Network-on-Chips.” in IEEE Transactions on Parallel and Distributed Systems (TPDS) doi: 10.1109/TPDS.2020.2968068. TPDS is a top journal for the presentation of research results on parallel and distributed computing systems. This paper introduces a hardware-software co-design to reduce the latency and power consumption of on-chip interconnect by approximating communication traffic while meeting applications’ requirements on data accuracy.

Prof. Ahmed Louri received a National Science Foundation award for the project “Neural Network Accelerators for Machine Learning” 

Dr. Ahmed Louri (ECE) and his research collaborators at Ohio University have been awarded a three-year, $1.1 million National Science Foundation grant for the project “Neural Network Accelerators for Machine Learning.” Dr. Louri is the principal investigator on the grant, and his share of the award is $600,000. The overarching goal of this research is to design highly parallel and energy-efficient neural network accelerators that can achieve 100x speed improvement over current state-of-the-art for a wide range of machine learning applications requiring large data sets, including finance, health, defense, and transportation, among several others. Apart from the technological, industrial, and intellectual impacts that could translate into benefits for society, the research also aims to have a major impact on education by integrating discovery with teaching and training.

Prof. Louri and his students, Ke Wang and Hao Zheng, filed 2 U.S. Non-Provisional Patent Applications.

The US Patent and Trademark Office filed two U.S. Non-Provisional Patents to Professor Ahmed Louri and his students.

1) Ke Wang and Ahmed Louri, Non-Proviaional Application No. 16/547,297,
Title: "Learning-Based High-Performance, Energy-Efficient, Fault-Tolerant On-Chip Communication Design Framework".

2) Hao Zheng and Ahmed Louri, Non-Proviaional Application No. 16/547,161,
Title: “EZ-Pass: An Energy Performance-Efficient Power-Gating Router Architecture for Scalable On-Chip Interconnect Architecture”. 

Ke Wang presented his paper in ISCA'19

Ke Wang attended the 46th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA’19), held June 22~26, Phoenix, Arizona. At the conference, he presented the paper "IntelliNoC: A Holistic Design Framework for Energy-Efficient and Reliable On-chip Communication for Manycores". The paper introduces a machine learning enabled design methodology for scalable manycore network on chips with the aim of balancing power consumption, reliability and performance. The paper was co-authored by his advisor Dr. Ahmed Louri (ECE), Dr. Avinash Karanth (Ohio University), and Razvan Bunescu (Ohio University).

Dr. Ahmed Louri (ECE) has been awarded a three-year $1.1 million National Science Foundation grant.

Dr. Ahmed Louri has been awarded a three-year $1.1 million National Science Foundation grant for the project “Photonic Neural Network Accelerator for Energy-efficient Heterogeneous Multicore Architectures.” Dr. Louri and his research team will leverage photonic technology’s (device and architecture) unique properties to design deep neural network accelerators for heterogeneous multicores to improve parallelism, energy-efficiency, and scalability for various machine learning applications. The proposed research bridges a very important gap between photonic technology, hardware architects, and machine learning. As such, and due to its cross-cutting nature, it will have a significant impact on the computer industry and far-reaching societal impacts.

Congratulations to Hao Zheng for winning the First place in engineering categorize at the GW research days

Congratulations to Hao Zheng, PhD student at HPCAT lab, for winning the first place in the Engineering categorize at the 24th GW Research Days, which is the largest research showcase at GWU. His contribution was on designing a high-performance, energy-efficient scalable multicore architecture.

Prof. Louri and his students, Ke Wang and Hao Zheng, filed 2 U.S. Provisional Patents.

The US Patent and Trademark Office filed two U.S. Provisional Patents to Professor Ahmed Louri and his students.

1) Ke Wang and Ahmed Louri, Provisional Application No. 62/720,634,
Title: "Reinforcement Learning for Fault-tolerant Energy-efficient NoC Design".

2) Hao Zheng and Ahmed Louri, Provisional Application No. 62/720,653,
Title: “EZ-PASS: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs”. 

Congrats to Ke Wang on his accepted ISCA 2019 paper!
(Acceptance Rate ~ 17%)

Congrats to our PhD student Ke Wang on his accepted International Symposium on Computer Architecture (ISCA) 2019 paper titled: “IntelliNoC: A Holistic Framework for Energy-Efficient and Reliable On-chip Communication for Manycores”. The work introduces an intelligent NoC design which balances the trade-offs among performance, power, and reliabity using reinforcement learning (RL).