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May, 2021

Prof. Louri Receives The George Washington University 2021 Office of the Vice-President for Research, Distinguished Researcher Award!

Congratulations to Prof. Ahmed Louri, who was selected to receive the GWU 2021 Office of the Vice-President for Research (OVPR), Distinguished Researcher Award. The OVPR Distinguished Researcher Award recognizes GWU faculty members who have made significant contributions in research and scholarship to the university and society. The award is given annually to just one GWU faculty member.

February, 2021

Congrats to Yuan on his accepted DAC paper!

Congrats to our PhD student Yuan Li on his accepted Design Automation Conference (DAC) 2021 paper: Yuan Li, Ahmed Louri, and Avinash Karanth, " Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects," which is to be appeared in proceedings of 58th Design Automation Conference (DAC), San Francisco, December 5-9, 2021. The Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits. DAC focuses on the latest methodologies and technology advancements in electronic design.

February, 2021

Congrats to Dr. Li on his accepted TSUSC paper!

Congrats to Dr. Jiajun Li on his accepted paper: Jiajun Li and Ahmed Louri, "AdaPrune: An Accelerator-aware Pruning Technique for Sustainable CNN Accelerators", which is accepted to publish in IEEE Transactions on Sustainable Computing, DOI: 10.1109/TSUSC.2021.3060690, 2021.

September, 2020

Yuechen presented his paper in CODES+ISSS! 

Dr. Ahmed Louri (ECE) and his Ph.D. students, Yuchen, presented the paper “Learning-based Quality Management for Approximate Communication in Network-on-Chips” at International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), held September 20-25, 2020.

June, 2020

Congrats to Cory and Hao on their accepted IEEE Micro paper!” 

Dr. Ahmed Louri (ECE) and his Ph.D. students, Ke Wang and Hao Zheng, have published a refereed journal paper: K. Wang, H. Zheng, and A. Louri. “TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-On-Chip Architecture,” IEEE Micro: Special Issue on Machine Learning for Systems, DOI: 10.1109/MM.2020.3003576, June 2020. The work exploits the use of machine learning to detect hardware Trojans in Network-on-Chip and presents a high-performance and energy-efficient design for threat mitigation.

April, 2020

Congrats to Cory on his accepted TPDS paper!” 

Dr. Ahmed Louri (ECE) and his Ph.D. student Ke Waing have published the following paper: K. Wang and A. Louri. “CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning,” IEEE Transactions on Parallel and Distributed Systems. DOI: 10.1109/TPDS.2020.2986297. The work exploits the use of reinforcement learning and presents a Network-on-Chip design that simultaneously reduces network latency, improves energy-efficiency, and tolerates transient errors and permanent faults. This research is funded by a grant from the National Science Foundation.

January, 2020

Congrats to Yuechen Chen on his accepted TPDS paper!” 

Dr. Ahmed Louri (ECE) and his Ph.D. student Yuechen Chen have published the following paper: Y. Chen and A. Louri, “An Approximate Communication Framework for Network-on-Chips.” in IEEE Transactions on Parallel and Distributed Systems (TPDS) doi: 10.1109/TPDS.2020.2968068. TPDS is a top journal for the presentation of research results on parallel and distributed computing systems. This paper introduces a hardware-software co-design to reduce the latency and power consumption of on-chip interconnect by approximating communication traffic while meeting applications’ requirements on data accuracy.

Nov, 2019

Dr. Ahmed Louri's paper was accepted by HPCA2020

Dr. Ahmed Louri's paper, "PIXEL: Photonic Neural Network Accelerator", was accepted by the 26th International Symposium on High-Performance Computer Architecture (HPCA'20). HPCA is recognized as the premier forum for scientists and engineers to present their latest research findings in this rapidly-changing field. HPCA'20 will be held at San Diego, CA on February 22-26, 2020.

Sep 9, 2019

Prof. Ahmed Louri received a National Science Foundation award for the project “Neural Network Accelerators for Machine Learning” 

Dr. Ahmed Louri (ECE) and his research collaborators at Ohio University have been awarded a three-year, $1.1 million National Science Foundation grant for the project “Neural Network Accelerators for Machine Learning.” Dr. Louri is the principal investigator on the grant, and his share of the award is $600,000. The overarching goal of this research is to design highly parallel and energy-efficient neural network accelerators that can achieve 100x speed improvement over current state-of-the-art for a wide range of machine learning applications requiring large data sets, including finance, health, defense, and transportation, among several others. Apart from the technological, industrial, and intellectual impacts that could translate into benefits for society, the research also aims to have a major impact on education by integrating discovery with teaching and training.

August, 2019

Dr. Ahmed Louri was recently awarded the IEEE Outstanding Leadership Award

Dr. Ahmed Louri was recently awarded the IEEE Outstanding Leadership Award for his leadership to the field and for serving as the General Chair of the 21st IEEE International Conference on High Performance Computing and Communications (HPCC-2019). HPCC-2019 was part of the IEEE International Conferences HPCC/DSS/SmartCity-2019, which were held in August in Zhangjiajie, China. IEEE is the world’s largest technical professional organization for the advancement of technology.

Aug 22, 2019

Prof. Louri and his students, Ke Wang and Hao Zheng, filed 2 U.S. Non-Provisional Patent Applications.

The US Patent and Trademark Office filed two U.S. Non-Provisional Patents to Professor Ahmed Louri and his students.

1) Ke Wang and Ahmed Louri, Non-Proviaional Application No. 16/547,297,
Title: "Learning-Based High-Performance, Energy-Efficient, Fault-Tolerant On-Chip Communication Design Framework".

2) Hao Zheng and Ahmed Louri, Non-Proviaional Application No. 16/547,161,
Title: “EZ-Pass: An Energy Performance-Efficient Power-Gating Router Architecture for Scalable On-Chip Interconnect Architecture”. 

June 26~28, 2019

Yuechen Chen presented his paper in ICS'19

Yuechen Chen attended the 33rd ACM International Conference on Supercomputing (ICS), held June 26-28, Phoenix, AZ. At the conference, he presented the paper "An Online Quality Management Framework for Approximate Communication in Network-on-Chips." This paper introduces a hardware-based quality management framework for the approximation system in network-on-chip to further enhance network performance while ensuring the quality of communication.

June 22~26, 2019

Ke Wang presented his paper in ISCA'19

Ke Wang attended the 46th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA’19), held June 22~26, Phoenix, Arizona. At the conference, he presented the paper "IntelliNoC: A Holistic Design Framework for Energy-Efficient and Reliable On-chip Communication for Manycores". The paper introduces a machine learning enabled design methodology for scalable manycore network on chips with the aim of balancing power consumption, reliability and performance. The paper was co-authored by his advisor Dr. Ahmed Louri (ECE), Dr. Avinash Karanth (Ohio University), and Razvan Bunescu (Ohio University).

June 3~5, 2019

Hao Zheng presented his paper in DAC'19

Hao Zheng attended the Design Automation Conference (DAC), held June 3~5, Las Vegas, NV. He presented his paper titled: “An Energy-efficient Network-On-Chip Design Using Reinforcement Learning”. The work introduces a proactive power mangement mechanism to optimize energy efficiency with reinforcement learning (RL).

May 13, 2019

Dr. Ahmed Louri (ECE) has been awarded a three-year $1.1 million National Science Foundation grant.

Dr. Ahmed Louri has been awarded a three-year $1.1 million National Science Foundation grant for the project “Photonic Neural Network Accelerator for Energy-efficient Heterogeneous Multicore Architectures.” Dr. Louri and his research team will leverage photonic technology’s (device and architecture) unique properties to design deep neural network accelerators for heterogeneous multicores to improve parallelism, energy-efficiency, and scalability for various machine learning applications. The proposed research bridges a very important gap between photonic technology, hardware architects, and machine learning. As such, and due to its cross-cutting nature, it will have a significant impact on the computer industry and far-reaching societal impacts.

April 15, 2019

Congrats to Yuechen Chen on his accepted ICS 2019 paper!

Congrats to our Ph.D. student Yuechen Chen on his accepted International Conference on Supercomputing (ICS) 2019 paper titled: “An Online Quality Management Framework for Approximate Communication in Network-on-Chips.” The work introduces a quality control method to achieve aggressive approximation with output quality guarantee.

April 10, 2019

Congratulations to Hao Zheng for winning the First place in engineering categorize at the GW research days

Congratulations to Hao Zheng, PhD student at HPCAT lab, for winning the first place in the Engineering categorize at the 24th GW Research Days, which is the largest research showcase at GWU. His contribution was on designing a high-performance, energy-efficient scalable multicore architecture.

April 10, 2019

Hao Zheng and Yuan Li have won the AccelerateGW I-Crops site grant at the GW research days!

Congratulations to Hao Zheng and Yuan Li, PhD students at HPCAT lab, for winning the AccelerateGW I-Crops site grant at the 24th GW Research Days, which is the largest research showcase at GWU. 

March, 2019

Prof. Louri and his students, Ke Wang and Hao Zheng, filed 2 U.S. Provisional Patents.

The US Patent and Trademark Office filed two U.S. Provisional Patents to Professor Ahmed Louri and his students.

1) Ke Wang and Ahmed Louri, Provisional Application No. 62/720,634,
Title: "Reinforcement Learning for Fault-tolerant Energy-efficient NoC Design".

2) Hao Zheng and Ahmed Louri, Provisional Application No. 62/720,653,
Title: “EZ-PASS: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs”. 

March 29, 2019

Our DATE paper was nominated for Best Paper Award!

The Design Automation & Test in Europe Conference & Exhibition (DATE) was held in Florence, Italy from 25 to 29 March 2019. On the final day of the conference, our paper was nominated for Best Paper Award of DATE 2019 along with 20 other papers, selected from 202 accepted papers. Congratulations to Ke Wang!

March 16, 2019

Congrats to Ke Wang on his accepted ISCA 2019 paper!
(Acceptance Rate ~ 17%)

Congrats to our PhD student Ke Wang on his accepted International Symposium on Computer Architecture (ISCA) 2019 paper titled: “IntelliNoC: A Holistic Framework for Energy-Efficient and Reliable On-chip Communication for Manycores”. The work introduces an intelligent NoC design which balances the trade-offs among performance, power, and reliabity using reinforcement learning (RL).

March 1, 2019

Congrats to Hao Zheng on his accepted DAC 2019 paper!

Congrats to our PhD student Hao Zheng on his accepted Design Automation Conference (DAC) 2019 paper titled: “An Energy-efficient Network-On-Chip Design Using Reinforcement Learning”. The work introduces a proactive power mangement mechanism to optimize energy efficiency with reinforcement learning (RL). 

Dec 4, 2018

Dr. Louri receives new patent

The US Patent and Trademark Office granted Professor Ahmed Louri, David and Marylin Karlgaard Endowed Chair of ECE US Patent 10,148,593 Title: “Directional allocation of communication links based on data traffic loads”. This patent introduces interconnection links that have four functions: these links can dynamically function as (1) forward repeaters, (2) backward repeaters, (3) forward buffers, and (4) backward buffers. This enables significant power reduction while enabling circuits to both improve performance and reliability. 

Nov 20, 2018

Congrats to Ke Wang on his accepted DATE 2019 paper!
(Acceptance Rate ~ 24%)

Congrats to our PhD student Ke Wang on his accepted Design Automation & Test in Europe Conference & Exhibition (DATE) 2019 paper titled: “High-performance, Energy-efficient, Fault-tolerant Network-On-Chip Design Using Reinforcement Learning”. The work introduces a proactive fault-tolerant mechanism to optimize energy efficiency and performance with reinforcement learning (RL).

Nov 19, 2018

Dr. Louri appointed chair of Computer Society committee

The IEEE Computer Society Board of Governors has appointed Dr. Ahmed Louri chair of the Computer Society’s 2019 Fellow Evaluating Committee. The IEEE Fellow Evaluating Committee must determine whether the work of each candidate is recognized and considered outstanding in the Computer Society's field of interest. Based on the recommendation of the Fellow Committee, the IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an extraordinary record of accomplishments in any of the IEEE fields of interest. The total number selected for the grade of Fellow in any one year does not exceed one-tenth of one percent of the total voting Institute membership. 

Aug 6, 2018

Congrats to Yuechen Chen and Dr. Md Farhadur Reza on their accepted ICCD 2018 paper!

Congrats to our Ph.D. student Yuechen Chen and Dr. Md Farhadur Reza on their accepted ICCD 2018 paper titled: “DEC-NoC: An Approximate Framework based on Dynamic Error Control with Applications to Energy-efficient NoCs”. The work introduces a dynamic error control scheme, which reduces the amount of error checking and correction in packet transmission based on application's error tolerance to enhance energy efficiency and performance.

Jul 24, 2018

Dr. Ahmed Louri and his research team has published a seminal conference paper titled: “LEAD: Learning-enabled Energy-Aware Dynamic Voltage/Frequency Scaling in NoC”

Professor Ahmed Louri and his research team has published a seminal conference paper titled: “LEAD: Learning-enabled Energy-Aware Dynamic Voltage/Frequency Scaling in NoC”. The work introduces machine learning techniques to manage power management in network on chips for future computing systems.

Jul 6, 2018

Dr. Ahmed Louri and his research team published a seminal paper for scaling future computing chips to thousands of processors (or cores) on a single chip at a flagship conference on parallel computing

Dr. Ahmed Louri and his research team published a seminal paper for scaling future computing chips to thousands of processors (or cores) on a single chip at a flagship conference on parallel computing. The paper is titled “Power-Efficient Kilo-Core Photonic-Wireless Hybrid Network on Chips,” was presented at the 32nd IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Vancouver, BC, May 21-25, 2018.

Jul 6, 2018

Dr. Ahmed Louri has been appointed the Editor-in-Chief of the IEEE Transactions on Computers

Prof. Ahmed Louri has been appointed the Editor-in-Chief (EIC) of the IEEE Transactions on Computers (TC). His appointment will start January 2019 for an initial period of 3 years and is renewable for a second two-year term. The IEEE TC is the leading refereed journal in the field of computing and the flagship publication of the IEEE Computer Society. IEEE TC has been serving the computing community for over 66 years. Excellence in scholarship and the highest publication standard has made TC the most respected and lead publication in computing.

May 18, 2018

Prof. Ahmed Louri received a National Science Foundation award for the project “Integrated Framework for System-level Approximate Computing” 

The project is a three-year collaborative effort with Dr. Fabrizio Lombardi (Northeastern University). The total amount of funding is $487,000, and GW’s portion is $262,000. In this research, Dr. Louri and his team seek to investigate and improve the advances and unique advantages of approximate computing to develop systems in both hardware and software (algorithms) that are low-power, high performance, and error-configurable. 

HPCAT Lab
High Performance Computing Architectures & Technologies Lab

Department of Electrical and Computer Enginnering
School of Engineering and Applied Science
The George Washington University


800 22nd Street NW
Washington, DC 20052
United States of America 

Contact

Ahmed Louri, IEEE Fellow
David and Marilyn Karlgaard Endowed Chair Professor of ECE
Director,  HPCAT Lab 


Email: louri@gwu.edu                    
Phone: +1 (202) 994 8241