F. Lombardi, Z. Wang, S. Liu, P. Reviriego, A. Louri, and Fabrizio Lombardi, "ASIC Design of Nanoscale Artificial Neural Networks for Inference/Training by Floating-Point Arithmetic,” in IEEE Transactions on Nanotechnology, vol. 23, pp. 208-216, February 2024.
Y. Li, A. Louri, and A. Karanth, "MERIT: A Sustainable DNN Accelerator Design with Photonic Phase-Change Memory," in IEEE Transactions on Sustainable Computing (TSUSC), early access, pp. 1-12, December 2024.
Z. Wang, F. Niknia, S. Liu, P. Reviriego, A. Louri, and F. Lombardi, "Fault Tolerance in Triplet Network Training: Analysis, Evaluation and Protection Methods" in IEEE Transactions on Emerging Topics in Computing (TETC), pp. 1–10, doi: 10.1109/TETC.2024.3481962, October 2024.
Y. Chen, A. Louri, S. Liu, and F. Lombardi, "A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training," in IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1–14, doi: 10.1109/TCSI.2024.3430831, 2024.
Y. Zhao, K. Wang, and A. Louri, "OPT-GCN: A Unified and Scalable Chiplet-based Accelerator for High-Performance and Energy-Efficient GCN Computation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), May 2024.
J. Yang, H. Zheng, and A. Louri, "Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration," in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 35, no. 2, pp. 349-361, February 2024.
Y. Chen, A. Louri, F. Lombardi, and S. Liu, "Chiplet-GAN: Chiplet-based Accelerator Design for Scalable Generative Adversarial Network Inference," in IEEE Circuits and System Magazine, vol. 24, no. 3, pp. 19-33, DOI: 10.1109/MCAS.2024.3359571, third quarter 2024.
Y. Li, A. Louri, and A. Karanth, "A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration," in IEEE Transactions on Parallel and Distributed Systems (TPDS), DOI: 10.1109/TPDS.2023.3327535, October 2023. [PDF]
K. Wang, H. Zheng, J. Li, and A. Louri, "Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration," in IEEE Transactions on Sustainable Computing (TSUSC), DOI: 10.1109/TSUSC.2023.3313880, September 2023. [PDF]
J. Li, K. Wang, H. Zheng, and A. Louri, "GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators," in Journal of Computer Science and Technology, vol. 38, no. 1, pp. 115-127, February 2023. [PDF]
Y. Chen, A. Louri, S. Liu, and F. Lombardi, "Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips," in IEEE Transactions on Sustainable Computing, vol. 8, no. 1, pp. 120-132, January 2023. [PDF]
J. Li, H. Zheng, K. Wang, and A. Louri, "SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator with Workload Balancing," in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 33, no. 11, pp. 2834-2845, DOI: 10.1109/TPDS.2021.3133691, November 2022. [PDF]
K. Wang, H. Zheng, Y. Li, and A. Louri, "SecureNoC: A Learning-enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design," in IEEE Transactions on Sustainable Computing, pp. 1-15, DOI: 10.1109/TSUSC/2021.3138279, December 2021. [PDF]
Y. Li, A. Louri, and A. Karanth, "SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-based Accelerator with Photonic Interconnects for CNN Inference," in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 33, no. 10, pp. 2332-2345, DOI: 10.1109/TPDS/2021.3139015, October 2022. [PDF]
Y. Li, K. Wang, H. Zheng, A. Louri, and A. Karanth, "ASCEND: A Scalable and Energy-Efficient DNN Accelerator with Photonic Interconnects," in IEEE Transactions on Circuits and Systems I: Regular Paper, pp. 1-12, DOI: 10.1109/TCSI.2022.3169953, May 2022. [PDF]
Y. Chen, S. Liu, F. Lombardi, and A. Louri, "A Technique for Approximate Communication in Network-on-Chips for Image Classification," TechRxiv Preprint, pp. 1-17, DOI: https://doi.org/10.36227/techrxiv.16438506.v1, August 2021. [PDF]
Y. Chen, S. Liu, F. Lombardi, and A. Louri, "A Technique for Approximate Communication in Network-on-Chips for Image Classification," in IEEE Transactions on Emerging Topics in Computing (TETC), DOI: 10.1109/TETC.2022.3162165, March 2022. [PDF]
J. Li and A. Louri, "AdaPrune: An Accelerator-aware Pruning Technique for Sustainable CNN Accelerators", in IEEE Transactions on Sustainable Computing, vol. 7, no. 1, pp. 47-60, DOI: 10.1109/TSUSC.2021.3060690, January 2022. [PDF]
Y. Chen, and A. Louri, “Learning-based Quality Management for Approximate Communication in Network-on-Chips”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), September, 2020. [PDF]
Z. Wang, F. Niknia, S. Liu, P. Reviriego, A. Louri, and F. Lombardi, "Stuck-at-Faults in Triplet Network Training: Analysis, Evaluation and Protection Methods," submitted to IEEE Transactions on Emerging Topics in Computing.
F. Niknia, Z. Wang, S. Liu, P. Reviriego, A. Louri, and F. Lombardi, "ASIC Design of Nanoscale Artificial Neural Networks for Inference/Training by Floating-Point Arithmetic," in IEEE Transactions on Nanotechnology, February 2024.
Q. Fettes, K. Shiflett, A. Karanth, R. Bunescu and A. Louri, “Hardware-Level Thread Migration to Reduce On-Chip Data Movement with Reinforcement Learning,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), September, 2020. [PDF]
K. Wang, H. Zheng, and A. Louri, “TSA: Learning-Based Threat Detection and Mitigation for Secure System-On-Chip Architectures”, in IEEE Micro, DOI: 10.1109/MM.2020.3003576, June 2020. [PDF]
H. Zheng and A. Louri, “Agile: A Learning-enabled Power and performance-Efficient Network-on-Chip Design”, in IEEE Transactions on Emerging Topics in Computing (TETC), DOI: 10.1109/TETC.2020.3003496, June 2020. [PDF]
K. Wang and A. Louri, “CURE: High-Performance, Low-Power, Fault-Secure Network-on-Chip Architecture Using Reinforcement Learning”, in IEEE Transactions on Parallel and Distributed Computers (TPDS), DOI: 10.1109/TPDS.2020.2986297, April 2020. [PDF]
Y. Li, and A. Louri, "ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures", in IEEE Transactions on Sustainable Computing, DOI: 10.1109/TSUSC.2020.2981340, March 2020. [PDF]
Y. Chen, and A. Louri, “An Approximate Communication Framework for Network-on-Chips,” in IEEE Transactions on Parallel and Distributed Systems, vol.31, issue. 6, pp. 1434 - 1446, June 2020. [PDF]
Z. Wang, F. Niknia, S. Liu, P. Reviriego, A. Louri, and F. Lombardi, "Fault Tolerant Triplet Networks for Training and Inference," TechRxiv. Preprint, https://doi.org/10.36227/techrxiv.21251904.v1, October 2022. [PDF]
F. Niknia, Z. Wang, S. Liu, A. Louri, and F. Lombardi, "Nanoscale Accelerators for Artificial Neural Networks," in IEEE Nano Technology Magazine, vol. 16, no. 6, pp. 14-21, December 2022. [PDF]
K. Chen, W. Liu, A. Louri, and F. Lombardi, "A Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation", IEEE Open Journal of Nanotechnology, vol. 3, pp. 36-44, DOI: 10.1109/OJNANO.2022.3153329, February 2022. [PDF]
X. Tang, S. Liu, F. Niknia, P. Reviriego, W. Tang, A. Louri, and F. Lombardi, "A Delta Sigma Modulator based Stochastic Divider," IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2022.3168286, January 2022. [PDF]
S. Liu, P. Reviriego, A. Ullah, A. Louri, and F. Lombardi, "Error-Resilient Data Compression with Tunstall Codes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 5, pp. 1963-1975, May 2023. [PDF]
S. Liu, K. Chen, P. Reviriego, W. Liu, A. Louri, and F. Lombardi, "Reduced Precision Redundancy for Reliable Processing of Data," in IEEE Transactions on Emerging Topics in Computing (TETC), vol. 9, no. 04, pp. 1960-1971, DOI: 10.1109/TETC.2019.2947617, October 2021. [PDF]
S. Liu, X. Tang, F. Niknia, P. Reviriego, W. Liu, A. Louri, and F. Lombardi, "Stochastic Dividers for Low Latency Neural Networks", in IEEE Transactions on Circuits and Systems I, vol. 68, issue 10, pp. 4102-4115, DOI: 10.1109/TCSI.2021.3103926, October 2021. [PDF]
T. F. Canan, S. Kaya, A. Karanth, and A. Louri, “Ultra-Compact and Low-Power Logic Circuits via Work-Function Engineering,” in IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 5, issue. 2, pp. 94-102, December 2019. [PDF]
S. Liu, K. Chen, P. Reviriego, W. Liu, A. Louri and F. Lombardi, “Reduced Precision Redundancy for Error Tolerance and Reliable Processing of Data,” in IEEE Transactions on Emerging Topics in Computing (TETC), DOI :10.1109/TETC.2019.2947617, 2019. [PDF]
A. Sikder, A. Kodi, S. Kaya, D. Carbaugh, S. Laha, A. Louri, H. Xin and J. Wu, “Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies,” in IEEE Transactions on Sustainable Computing, vol. 4, no. 3, pp. 293-307, 1 July-Sept. 2019. [PDF]
D. Machovec, B. Khemka, N. Kumbhare, S. Pasricha, A. A. Maciejewski, H. J. Siegel, A. Akoglu, G. A. Koenig, S. Hariri, M. Wright, M. Hilton, R. Rambharos, C. Blandin, S. Hariri, C. Tunc, A. Louri and N. Imam, “Utility-Based Resource Management in an Oversubscribed Energy-Constrained Heterogeneous Environment Executing Parallel Applications,” in Parallel Computing, Vol. 83, pp. 48-72, Apr. 2019. [PDF]
A. Louri, J. Collet and A. Karanth, “Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs,” in ACM Journal of Emerging Technologies for Computing, Volume 15, Issue 1, pp.4, February 2019. [PDF]
Q. Fettes, M. Clark, R. Bunescu, A. Karanth, and A. Louri, “Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques,” in IEEE Transactions on Computers (TC), Volume 68, Issue 3, pp.375-389 , March 2019. [PDF]
T. F. Canan, S. Kaya, A. Karanth, A. Louri, and H. Xin “Ambipolar SB-FinFETs: A New Path to Ultra-Compact sub-10nm Logic Circuits,” in IEEE Transactions on Electron Devices (TED), vol. 65, no. 12, 2018. [PDF]
H. Zheng and A. Louri, “EZ-Pass: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs,” in IEEE Computer Architecture Letters (CAL), vol. 17, no. 1, pp. 88-91, Jan. 2018. [PDF]
J. Wu, A. K. Kodi, S. Kaya, A. Louri and H. Xin, “Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications,” in IEEE Transactions on Antennas and Propagation, vol. 65, no. 12, pp. 6838-6846, Dec. 2017. [PDF]
P. Poluri and A. Louri, “Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors,” in IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 10, pp. 3058-3070, Oct. 2016. [PDF]
W. T. Wu and A. Louri, “A Methodology for Cognitive NoC Design,” in IEEE Computer Architecture Letters, vol. 15, no. 1, pp. 1-4, Jan.-June 2016. [PDF]
D. DiTomaso, A. K. Kodi, A. Louri and R. Bunescu, “Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures,” in IEEE Transactions on Computers, vol. 64, no. 12, pp. 3555-3568, Dec. 2015. [PDF]
T. J. Kao and A. Louri, “Optical Multilevel Signaling for High Bandwidth and Power-Efficient On-Chip Interconnects,” in IEEE Photonics Technology Letters, vol. 27, no. 19, pp. 2051-2054, Oct. 2015. [PDF]
P. Poluri and A. Louri, “A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems,” in IEEE Computer Architecture Letters, vol. 14, no. 2, pp. 107-110, July-Dec. 2015. [PDF]
R. W. Morris, A. K. Kodi, A. Louri and R. D. Whaley, “Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration,” in IEEE Transactions on Computers, vol. 63, no. 1, pp. 243-255, Jan. 2014. [PDF]
Jin Sun, Roman Lysecky, Karthik Shankar, Avinash Kodi, Ahmed Louri, and Janet Roveda. “Workload Assignment Considering NBTI Degradation in Multi-Core Systems.” in ACM Journal on Emerging Technologies in Computing Systems, 10, 1, Article 4, Jan. 2014, 22 pages. [PDF]
D. DiTomaso, R. Morris, A. K. Kodi, A. Sarathy and A. Louri, “Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 11, pp. 2141-2154, Nov. 2013. [PDF]
A. Louri and A. K. Kodi. “Editorial: Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC),” in IEEE Journal of Parallel and Distributed Computing, 71, Article 5, May 2011, pp. 623-624.
A. K. Kodi and A. Louri, “Energy-Efficient and Bandwidth-Reconfigurable Photonic Networks for High-Performance Computing (HPC) Systems,” in IEEE Journal of Selected Topics in Quantum Electronics, vol. 17, no. 2, pp. 384-395, Mar.-Apr. 2011.
A. K. Kodi, R. Morris and A. Louri, “Propel: Power and Area-Efficient Nanophotonic On-Chip Interconnect Architecture for Multicores,” in IEEE Journal of Selected Topics in Quantum Electronics, 2010.
A. K. Kodi and A. Louri, “Multidimensional and Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems,” in Journal of Lightwave Technology, vol. 27, no. 21, pp. 4634-4641, Nov. 2009.
A. K. Kodi and A. Louri, “Reconfigurable and Adaptive Photonic Networks for High-Performance Computing Systems,” in Applied Optics, Special Issue on Optical High-Performance Computing, vol. 48, no. 22, pp. E13-E23, Aug. 2009.
A. K. Kodi, A. Sarathy and A. Louri, “Adaptive Channel Buffers in On-Chip Interconnection Networks — A Power and Performance Analysis,” in IEEE Transactions on Computers, vol. 57, no. 9, pp. 1169-1181, Sept. 2008.
A. Sarathy, A. K. Kodi and A. Louri, “Low-power low-area network-on-chip architecture using adaptive electronic link buffers,” in Electronics Letters, vol. 44, no. 8, pp. 512-513, Apr. 2008.
A. K. Kodi and A. Louri, “Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems,” in IEEE Micro, vol. 28, no. 5, pp. 22-36, Sept.-Oct. 2008.
A. K. Kodi and A. Louri, “System simulation methodology of optical interconnects for high-performance computing systems,” in Journal of Optical Networking, vol. 6, no. 12, pp. 1282-1300, Dec. 2007.
C. Kochar, A. Kodi and A. Louri, “Proposed Low-Power High-Speed Microring Resonator-Based Switching Technique for Dynamically Reconfigurable Optical Interconnects,” in IEEE Photonics Technology Letters, vol. 19, no. 17, pp. 1304-1306, Sept. 2007.
C. Kochar, A. K. Kodi and A. Louri, “nD-RAPID: A multidimensional scalable fault-tolerant optoelectronic interconnection for high-performance computing systems,” in Journal of Optical Networking, Special Issue on Switching in Photonics, vol. 6, no. 5, pp. 465-481, May 2007.
A. K. Kodi and A. Louri, “RAPID for high-performance computing systems: architecture and performance evaluation,”in Applied Optics, Special Issue on Information Photonics, vol. 45, no. 25, pp. 6326-6334, Sept. 2006.
A. K. Kodi and A. Louri, “Design of a high-speed optical interconnect for scalable shared-memory multiprocessors,” in IEEE Micro, vol. 25, no. 1, pp. 41-49, Jan.-Feb. 2005.
A. Louri and A. K. Kodi, “An optical interconnection network and a modified snooping protocol for the design of large-scale symmetric multiprocessors (SMPs),” in IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 12, pp. 1093-1104, Dec. 2004.
A. K. Kodi and A. Louri, “RAPID: reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors,” in Journal of Lightwave Technology, vol. 22, no. 9, pp. 2101-2110, Sept. 2004.
R. Bhagavatula and A. Louri, “An Optically Assisted High Speed Scalable IP Router,” in IEEE Optical Communications, 2004.
A. Louri and A. K. Kodi, “SYMNET: an optical interconnection network for scalable high-performance symmetric multiprocessors,” in Applied Optics, vol. 42, no. 17, pp. 3407-3417, June 2003.
A. Louri and A. K. Kodi, “Parallel optical interconnection network for address transactions in large-scale cache coherent symmetric multiprocessors,” in IEEE Journal of Selected Topics in Quantum Electronics, Special Issue on Optical Interconnects, vol. 9, no. 2, pp. 667-676, Mar.-Apr. 2003.
A. Louri and A. K. Kodi, “Scalable Optical Interconnection Networks for Symmetric Multiprocessors (SMPs)”, in Optics in Information Systems, SPIE’s International Technical Group Newsletter, vol. 14, no. 1, pp. 7-8, Mar. 2003.
P. Y. Choo and A. Louri, “Guided-wave multiwavelength polarization-insensitive processing module for a parallel multicomparand perfect-match algorithm,” in Optics Letters, vol. 25, no. 20, pp. 1541-1543, Oct. 2000.
B. Webb and A. Louri, “A class of highly scalable optical crossbar-connected interconnection networks (SOCNs) for parallel computing systems,” in IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 5, pp. 444-458, May 2000.
A. Detofsky, P. Y. Choo and A. Louri, “Equivalency-Processing Parallel Photonic Integrated Circuit (EP3IC): equivalence search module based on multiwavelength guided-wave technology,” in Applied Optics, Special Issue on Optics in Computing, vol. 39, no. 5, pp. 818-826, Feb. 2000.
J.H. Collet, D. Litaize, J. V. Campenhut, C. Jesshope, M. Desmulliez, H. Thienpont, J. Goodman and A. Louri, “Architectural approach to the role of optics in monoprocessor and multiprocessor machines,” in Applied Optics, Special Issue on Optics in Computing, vol. 39, no. 5, pp. 671-682, Feb. 2000.
P. Y. Choo, A. Detofsky and A. Louri, “Multiwavelength optical content-addressable parallel processor for high-speed parallel relational database processing,” in Applied Optics, vol. 38, no. 26, pp. 5594-5604, Sept. 1999.
B. Webb and A. Louri, “All-optical crossbar switch using wavelength division multiplexing and vertical-cavity surface-emitting lasers,” in Applied Optics, vol. 38, no. 29, pp. 6176-6183, Oct. 1999.
A. Detofsky, P. Y. Choo and A. Louri, “Optical implementation of a constant-time multicomparand bit-parallel magnitude-comparison algorithm using wavelength - and polarization-division multiplexing with application to parallel database processing,” in Optics Letters, vol. 23, no. 17, pp. 1372-1374, Sept. 1998.
A. Louri, B. Weech and C. Neocleous, “A spanning multichannel linked hypercube: a gradually scalable optical interconnection network for massively parallel computing,” in IEEE Transactions on Parallel and Distributed Systems, vol. 9, no. 5, pp. 497-512, May 1998.
A. Louri and C. Neocleous, “Incrementally scalable optical interconnection network with a constant degree and constant diameter for parallel computing,” in Applied Optics, vol. 36, no. 26, pp. 6594-6604, Sept. 1997.
A. Louri and C. Neocleous, “A spanning bus connected hypercube: a new scalable optical interconnection network for multiprocessors and massively parallel systems,” in Journal of Lightwave Technology, vol. 15, no. 7, pp. 1241-1253, July 1997.
A. Louri and R. Gupta, “Hierarchical optical ring interconnection (HORN): scalable interconnection network for multiprocessors and multicomputers,” in Applied Optics, vol. 36, no. 2, pp. 430-442, Jan. 1997.
A. Louri, S. Furlonge and C. Neocleous, “Experimental demonstration of the optical multi-mesh hypercube: scaleable interconnection network for multiprocessors and multicomputers,” in Applied Optics, vol. 35, no. 35, pp. 6909-6919, Dec. 1996.
A. Louri and S. Furlonge, “Feasibility study of a scalable optical interconnection network for massively parallel processing systems,” in Applied Optics, vol. 35, no. 8, pp. 1296-1308, Mar. 1996.
A. Louri and H. K. Sung, “Optical binary de Bruijn networks for massively parallel computing: design methodology and feasibility study,” in Applied Optics, vol. 34, no. 29, pp. 6714-6722, Oct. 1995.
A. Louri and J. Na, “Design of an optical content-addressable parallel processor for expert systems,” in Applied Optics, vol. 34, no. 23, pp. 5053-5063, Aug. 1995.
A. Louri and M. C. Major, “Generalized methodology for modeling and simulating optical interconnection networks using diffraction analysis,” in Applied Optics, vol. 34, no. 20, pp. 4052-4064, July 1995.
A. Louri, J. Hatch and J. Na, “Constant-time parallel sorting algorithm and its optical implementation using smart pixels,” in Applied Optics, vol. 34, no. 17, pp. 3087-3096, June 1995.
A. Louri, J. A. Hatch and Jongwhoa Na, “A constant-time parallel sorting algorithm and its optical implementation,” in IEEE Micro, vol. 15, no. 3, pp. 60-71, June 1995.
A. Louri and J. A. Hatch, “Optical content-addressable parallel processor for high-speed database processing,” in Applied Optics, vol. 33, no. 35, pp. 8153-8163, Dec. 1994.
A. Louri and H. K. Sung, “Scalable optical hypercube-based interconnection network for massively parallel computing,” in Applied Optics, vol. 33, no. 32, pp. 7588-7598, Nov. 1994.
A. Louri and J. A. Hatch, “An optical associative parallel processor for high-speed database processing: theoretical concepts and experimental results,” in Computer, vol. 27, no. 11, pp. 65-72, Nov. 1994.
A. Louri and H. K. Sung, “3D optical interconnects for high-speed interchip and interboard communications,” in Computer, vol. 27, no. 10, pp. 27-37, Oct. 1994.
A. Louri and H. K. Sung, “An optical multi-mesh hypercube: a scalable optical interconnection network for massively parallel computing,” in Journal of Lightwave Technology, vol. 12, no. 4, pp. 704-716, Apr. 1994.
A. Louri and J. Na, “Modeling and simulation methodology for digital optical computing systems,” in Applied Optics, Special Issue on Optical Computing, vol. 33, no. 8, pp. 1549-1558, Mar. 1994.
B. P. Zeigler and A. Louri, “A Simulation Enviroment for Intelligent Machine Architectures,” in Journal of Parallel and Distributed Computing, vol. 18, no. 1, pp. 77-88, May 1993.
A. Louri and J. A. Hatch, “Optical implementation of a single-iteration thresholding algorithm with applications to parallel data-base/knowledge-base processing,” in Optics Letters, vol. 18, no. 12, pp. 992-994, June 1993.
A. Louri and J. Na, “Parallel electro-optical rule-based system for fast execution of expert systems,” in Applied Optics, vol. 32, no. 11, pp. 1863-1875, Apr. 1993.
A. Louri and A. Post, “Complexity analysis of optical-computing paradigms,” in Applied Optics, vol. 31, no. 26, pp. 5568-5583, Sept. 1992.
A. Louri, “Optical content-addressable parallel processor: architecture, algorithms, and design concepts,” in Applied Optics, vol. 31, no. 17, pp. 3241-3258, June 1992.
A. Louri, “Three-dimensional optical architecture and data-parallel algorithms for massively parallel computing,” in IEEE Micro, vol. 11, no. 2, pp. 24-27, Apr. 1991.
A. Louri, “Parallel implementation of optical symbolic substitution logic using shadow-casting and polarization,” in Applied Optics, vol. 30, no. 5, pp. 540-548, Feb. 1991.
A. Louri, “Throughput enhancement for optical symbolic substitution computing systems,” in Applied Optics, vol. 29, no. 20, pp. 2979-2981, July 1990.
A. Louri, “Efficient optical implementation method for symbolic substitution logic using shadow casting,” in Applied Optics, vol. 28, no. 16, pp. 3264-3267, Aug. 1989.
A. Louri, “A parallel architecture and algorithms for optical computing,” in Optics Communication, vol. 72, no. 1-2, pp. 27-36, July 1989.
K. Hwang and A. Louri, “Optical Multiplication And Division Using Modified-Signed-Digit Symbolic Substitution,” in Optical Engineering, Special Issue on Optical Computing, vol. 28, no. 4, pp. 364-372, Apr. 1989.
HPCAT Lab High Performance Computing Architectures & Technologies Lab
Department of Electrical and Computer Enginnering School of Engineering and Applied Science The George Washington University
800 22nd Street NW Washington, DC 20052 United States of America
Contact
Ahmed Louri, IEEE Life Fellow David and Marilyn Karlgaard Endowed Chair Professor of ECE Director, HPCAT Lab
