David and Marilyn Karlgaard Endowed Chair Professor of ECE
Director, HPCAT Laboratory
Editor-in-Chief, IEEE Transactions on Computers
Associate Editor, IEEE Transactions on Cloud Computing
Associate Editor, IEEE Transactions on Sustainable Computing
Congratulations to Prof. Ahmed Louri, who was selected to receive the GWU 2021 Office of the Vice-President for Research (OVPR), Distinguished Researcher Award. The OVPR Distinguished Researcher Award recognizes GWU faculty members who have made significant contributions in research and scholarship to the university and society. The award is given annually to just one GWU faculty member.
Prof. Ahmed Louri is the recipient of the IEEE Computer Society 2020 Edward J. McCluskey Technical Achievement Award, “for pioneering contributions to the solution of on-chip and off-chip communication problems for parallel computing and manycore architectures.” (Award Video)
We rely on computing in the design of systems for energy, transportation, finance, education, health, defense, entertainment, and overall wellness. However, today's computing systems are facing major challenges both at the technology and application levels. At the technology level, traditional scaling of device sizes has slowed down and the reduction of cost per transistor is plateauing, making it increasingly difficult to extract more computer performance by employing more transistors on-chip. Power limits and reduced semiconductor reliability are making device scaling more difficult – if not impossible – to leverage for performance in the future and across all platforms, including mobile, embedded systems, laptops, servers, and datacenters. Simultaneously, at the application level, we are entering a new computing era that calls for a migration from an algorithm computing world to a learning-based, data-intensive computing paradigm in which human capabilities are scaled and magnified. To meet the ever-increasing computing needs and to overcome power density limitations, the computing industry has embraced parallelism (parallel computing) as the only method for improving computer performance. Today, computing systems are being designed with tens to hundreds of computing cores integrated into a single chip and hundreds to thousands of computing servers based on these chips are connected in datacenters and supercomputers. However, power consumption remains a significant design problem, and such highly parallel systems still face major challenges in terms of energy efficiency, performance, and reliability.
Professor Louri and his team investigate novel parallel computer architectures and technologies which deliver high reliability, high performance, and energy-efficient solutions to important application domains and societal needs. The research has far-reaching impacts on the computing industry and society at large. Current research topics include: (1) the use of machine learning techniques for designing energy-efficient, reliable multicore architectures, (2) scalable accelerator-rich reconfigurable heterogeneous architectures, (3) emerging interconnect technologies (photonic, wireless, RF, hybrid) for network-on-chips (NoCs) & embedded systems, (4) future parallel computing models and architectures including Convolutional Neural Networks (CNNs), Deep Neural Networks (DNNs), near data computing, approximate computing, and (5) cloud and edge computing.
1) Hao Zheng, Ke Wang, and Ahmed Louri. "Interconnection Network with Adaptable Router Lines for Chiplet-Based Manycore Architecture." Patent No. US 11,489,788 (Link).
2) Ahmed Louri and Yuechen Chen. "Systems and Methods for Approximate Communication Framework for Networks-on-Chips." Patent No. US 11,483,256 (Link).
3) Hao Zheng and Ahmed Louri. "EZ-Pass: An Energy Performance-Efficient Power-Gating Router Architecture for Scalable On-Chip Interconnect Architecture." Patent No. US 11,502,934 (Link).
1) Yingnan Zhao, "FSA: An Efficient Fault-Tolerant Systolic Array-based DNN Accelerator Architecture", 40th IEEE International Conference on Computer Design (ICCD), October 23-26, 2022, Lake Tahoe, CA.
2) Yuechen Chen, "Approximate Network-on-Chips with Application to Image Classification", 16th IEEE International Conference on Networking, Architecture, and Storage (NAS), October 3-4, Philadelphia, PA.
3) Jiaqi Yang, "Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation", 32nd Great Lakes Symposium on VLSI (GLSVLSI), June 6-8, Irvine, CA.