Tightly integrating stacked memory and processor dies in a 2.5D chiplet architecture is a promising approach to alleviate the memory wall problem. However, current stacked DRAM often cannot accommodate the entire datasets of modern applications due to capacity limitation, inevitably leading to slow and energy-consuming off-package memory accesses. An in-package heterogeneous memory architecture, which contains both stacked DRAM and denser stacked non-volatile memory (NVM), can overcome this capacity limitation. The resulting heterogeneous in-package memory architecture prompts the design of effective memory management schemes, as NVM typically performs worse than DRAM. We observe that the existing heterogeneous memory management schemes do not work well in the in-package heterogeneous memory architectures because these schemes cannot actively respond to memory access pattern variations and exhibit excessive overhead such as OS interrupt and translation look-aside buffer (TLB) shootdown. In this project, we propose a new memory management scheme specifically optimized for in-package heterogeneous memory architectures.