Research Topic

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Emerging Memory Technologies and Architectures

Current Researchers: Yuan Li;

Recent 3D/2.5D integration and packaging techniques have enabled multiple memory stacks of different technologies (SRAM, DRAM, non-volatile memory, etc.) to be integrated in the same chiplet-based system with computation dies. Integrating memory stacks in chiplet-based systems opens up a new design space and prompts optimizations of memory architectures to leverage the abundant wiring resource of the silicon interposer and provide high memory bandwidth. Besides, as different memory technologies exhibit distinct performance characteristics (latency, write endurance, etc.) and power consumptions, combining multiple memory technologies efficiently in one system is a challenging and unresolved issue.

In this research project, we plan to examine the memory access patterns in the chiplet-based systems, and identify and solve the key memory design challenges in such systems. We are also interested in developing hardware/software techniques to efficiently manage data movement in the hybrid memory architectures, in order to leverage the benefits of different memory technologies while minimizing their drawbacks.

01.

Hybrid Memory Architecture Management

Tightly integrating stacked memory and processor dies in a 2.5D chiplet architecture is a promising approach to alleviate the memory wall problem. However, current stacked DRAM often cannot accommodate the entire datasets of modern applications due to capacity limitation, inevitably leading to slow and energy-consuming off-package memory accesses. An in-package heterogeneous memory architecture, which contains both stacked DRAM and denser stacked non-volatile memory (NVM), can overcome this capacity limitation. The resulting heterogeneous in-package memory architecture prompts the design of effective memory management schemes, as NVM typically performs worse than DRAM. We observe that the existing heterogeneous memory management schemes do not work well in the in-package heterogeneous memory architectures because these schemes cannot actively respond to memory access pattern variations and exhibit excessive overhead such as OS interrupt and translation look-aside buffer (TLB) shootdown. In this project, we propose a new memory management scheme specifically optimized for in-package heterogeneous memory architectures.

HPCAT Lab
High Performance Computing Architectures & Technologies Lab

Department of Electrical and Computer Enginnering
School of Engineering and Applied Science
The George Washington University


800 22nd Street NW
Washington, DC 20052
United States of America 

Contact

Ahmed Louri, IEEE Fellow
David and Marilyn Karlgaard Endowed Chair Professor of ECE
Director,  HPCAT Lab 


Email: louri@gwu.edu                    
Phone: +1 (202) 994 8241