Research Topic

Secure Communication for Manycores and Machine Learning Accelerators

Current Researcher: Dr. Ke Wang;

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During the past decade, hardware security has become an increasing challenge due to the proliferation of shared resources in modern computer architecture designs. These shared resources can unavoidably allow sensitive data to be leaked to malicious parties through side or covert channels. Side-channel attacks create and monitor disturbances of electronic systems through timing, power, current, and electromagnetic in order to leak information and covertly transmit data. Moreover, the malicious source that is performing hardware-targeting side-channel attacks are hard to be detected, since intruders simply monitor and modulate the convert channel without explicitly transferring data or exposing their traces.

In this research task, we comprehensively evaluate the microarchitecture designs of multicore architectures and explore hardware vulnerabilities to various side-channel attacks. This is followed by development efficient countermeasures against those attacks without adversely impacting system performance. The research topics include malicious node detection, secure on-chip data transmission, and learning-based side-channel attack mitigation. 

01.

K. Wang, H. Zheng, Y. Li, and A. Louri, "SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design", IEEE Transactions on Sustainable Computing, 7.3 (2022): 709-723.

We propose SecureNoC, a learning-based framework to enhance NoC security against Hardware Trojan (HT) attacks while holistically improving performance and power. The proposed framework enhances NoC security with several architectural innovations, namely a per-router HT detector, multi-function bypass channels (MBCs), and a lightweight data encryption design. Specifically, the threat detector uses an artificial neural network for runtime HT detection with high accuracy. The MBCs consist of a router bypass route and reconfigurable channel buffers which can efficiently isolate malicious nodes and reduce power consumption. The proposed data encryption design adapts to diverse traffic patterns and dynamically deploys novel lightweight encryption techniques for desired security goals with improved latency. Additionally, to balance the trade-offs and handle the dynamic interactions of the proposed dynamic designs, a proactive deep-Q-learning (DQL) control policy is proposed to simultaneously provide optimized NoC security, performance, and power consumption. Simulation studies using PARSEC benchmarks show that the proposed SecureNoC achieves 36 percent higher HT detection accuracy over state-of-the-art NoC security techniques while reducing network latency by 39 percent and energy consumption by 46 percent.

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02.

K. Wang, H. Zheng, Y. Li, J. Li, and A. Louri, "AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems", in Proceedings of Design, Automation & Test in Europe Conference & Exhibition, Antwerp, Belgium, March 14-23, 2022.

The security of manycore systems has become increasingly critical. In system-on-chips (SoCs), Hardware Trojans (HTs) manipulate the functionalities of the routing components to saturate the on-chip network, degrade performance, and result in the leakage of sensitive data. Existing HT detection techniques, including runtime monitoring and state-of-the-art learning-based methods, are unable to timely and accurately identify the implanted HTs, due to the increasingly dynamic and complex nature of on-chip communication behaviors. We propose AGAPE, a novel Generative Adversarial Network (GAN)-based anomaly detection and mitigation method against HTs for secured on-chip communication. AGAPE learns the distribution of the multivariate time series of a number of NoC attributes captured by on-chip sensors under both HT-free and HT-infected working conditions. The proposed GAN can learn the potential latent interactions among different runtime attributes concurrently, accurately distinguish abnormal attacked situations from normal SoC behaviors, and identify the type and location of the implanted HTs. Using the detection results, we apply the most suitable protection techniques to each type of detected HTs instead of simply isolating the entire HT-infected router, with the aim to mitigate security threats as well as reducing performance loss. Simulation results show that AGAPE enhances the HT detection accuracy by 19 percent, reduces network latency and power consumption by 39 percent and 30 percent, respectively, as compared to state-of-the-art security designs.

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03.

Ke Wang, Hao Zheng, Ahmed Louri. “TSA: Learning-Based Threat Detection and Mitigation for Secure System-On-Chip Architectures.”in IEEE Micro: Special Issue on Machine Learning for Systems, Sept/Oct, 2020

Network-on-chips (NoCs) are playing a critical role in modern multicore architecture, and NoC security has become a major concern. Maliciously implanted Hardware Trojans (HTs) inject faults into on-chip communications that saturate the network, resulting in the leakage of sensitive data via side channels and significant performance degradation. While existing techniques protect NoCs by detecting and isolating HT-infected components, they inevitably incur occasional inaccurate detection with considerable network latency and power overheads. We propose TSA-NoC, a learning-based design framework for secure and efficient on-chip communication. The proposed TSA-NoC uses an artificial neural network (ANN) for runtime HT-detection with higher accuracy. Furthermore, we propose a deep reinforcement learning (DRL)-based adaptive routing design for HT mitigation with the aim of minimizing network latency and maximizing energy-efficiency. Simulation results show that TSA-NoC achieves up to 97% HT-detection accuracy, 70% improved energy-efficiency, and 29% reduced network latency as compared to state-of-the-art HT-mitigation techniques.

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HPCAT Lab
High Performance Computing Architectures & Technologies Lab

Department of Electrical and Computer Enginnering
School of Engineering and Applied Science
The George Washington University

800 22nd Street NW
Washington, DC 20052
United States of America 

Contact

Ahmed Louri, IEEE Fellow
David and Marilyn Karlgaard Endowed Chair Professor of ECE
Director,  HPCAT Lab 


Email: louri@gwu.edu                    
Phone: +1 (202) 994 8241

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