Research Topic

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Security in Computer Architecture

Current Researcher: Ke Wang;

Mobirise

During the past decade, hardware security has become an increasing challenge due to the proliferation of shared resources in modern computer architecture designs. These shared resources can unavoidably allow sensitive data to be leaked to malicious parties through side or covert channels. Side-channel attacks create and monitor disturbances of electronic systems through timing, power, current, and electromagnetic in order to leak information and covertly transmit data. Moreover, the malicious source that is performing hardware-targeting side-channel attacks are hard to be detected, since intruders simply monitor and modulate the convert channel without explicitly transferring data or exposing their traces.

In this research task, we comprehensively evaluate the microarchitecture designs of multicore architectures and explore hardware vulnerabilities to various side-channel attacks. This is followed by development efficient countermeasures against those attacks without adversely impacting system performance. The research topics include malicious node detection, secure on-chip data transmission, and learning-based side-channel attack mitigation. 

01.

Ke Wang, Hao Zheng, Ahmed Louri. “TSA: Learning-Based Threat Detection and Mitigation for Secure System-On-Chip Architectures.”in IEEE Micro: Special Issue on Machine Learning for Systems,Sept/Oct, 2020

Network-on-chips (NoCs) are playing a critical role in modern multicore architecture, and NoC security has become a major concern. Maliciously implanted Hardware Trojans (HTs) inject faults into on-chip communications that saturate the network, resulting in the leakage of sensitive data via side channels and significant performance degradation. While existing techniques protect NoCs by detecting and isolating HT-infected components, they inevitably incur occasional inaccurate detection with considerable network latency and power overheads. We propose TSA-NoC, a learning-based design framework for secure and efficient on-chip communication. The proposed TSA-NoC uses an artificial neural network (ANN) for runtime HT-detection with higher accuracy. Furthermore, we propose a deep reinforcement learning (DRL)-based adaptive routing design for HT mitigation with the aim of minimizing network latency and maximizing energy-efficiency. Simulation results show that TSA-NoC achieves up to 97% HT-detection accuracy, 70% improved energy-efficiency, and 29% reduced network latency as compared to state-of-the-art HT-mitigation techniques.

02.

High-Performance, Energy-Efficient Countermeasures Against Side-Channel Attacks (SCA) for NoCs

As technology scales, Network-on-Chip (NoC) architectures have emerged as the prevailing communication fabric for on-chip communication that efficiently interconnect heterogeneous processing cores, last level of cache(s), memory controllers and I/O devices. However, as computing resources are dynamically shared, NoCs are becoming increasingly vulnerable to security threats via covert or side channels. Conventional security designs against side-channel attacks (SCA) are costly in energy and adversely affacts performance. Our approach will explore the use of machine learning algorithms to design a high-performance and energy-efficient countermesure against side-channel attacks with dynamic granularity for protection (at the level of packets, flows, inter-core/inter-processor traffic and so on). 

HPCAT Lab
High Performance Computing Architectures & Technologies Lab

Department of Electrical and Computer Enginnering
School of Engineering and Applied Science
The George Washington University


800 22nd Street NW
Washington, DC 20052
United States of America 

Contact

Ahmed Louri, IEEE Fellow
David and Marilyn Karlgaard Endowed Chair Professor of ECE
Director,  HPCAT Lab 


Email: louri@gwu.edu                    
Phone: +1 (202) 994 8241