Publications

Journal Papers
 Conference Papers Book Chapters
  • Jiaqi Yang, Hao Zheng, and Ahmed Louri, "Aurora: A Versatile and Flexible Accelerator for Generic Graph Neural Networks," to appear in Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, CA, May 27-31, 2024.
  • Yingnan Zhao, Ke Wang, and Ahmed Louri, "An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference," to appear in Proceedings of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, June 23-27, 2024.
  • Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, and Hao Zheng, "VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design," to appear in Proceedings of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, June 23-27, 2024.
  • Farzad Niknia, Ziheng Wang, Shanshan Liu, Pedro Reviriego, Ahmed Louri, and Fabrizio Lombardi, "Floating-Point Formats and Arithmetic for Highly Accurate Multi-Layer Perceptrons," in Proceedings of the IEEE International Conference on Nanotechnology (NANO), Jeju City, Korea, July 2-5, 2023.
  • Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, and Hao Zheng, "Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration," to appear in IEEE International Conference on Computer Design (ICCD), Washington, DC, November 6-8, 2023.
  • Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, and Hao Zheng, "ARIES: Accelerating Distributed Training in Chiplet-based Systems via Flexible Interconnects," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, October 29-November 2, 2023.
  • Yuan Li, Ahmed Louri, and Avinash Karanth, "A Silicon Photonic Multi-DNN Accelerator," in Proceedings of IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Vienna, Austria, October 21-25, 2023.
  • Kyle Shiflett, Avinash Karanth, Razvan Bunescu, and Ahmed Louri, "Flumen: Dynamic Processing in the Photonic Interconnect," in Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), Orlando, FL, June 17-21, 2023. [PDF]
  • Yuan Li, Ahmed Louri, and Avinash Karanth, "Efficient Multicast Communication in Silicon Photonics Enhanced DNN Acceleration," in Proceedings of the IEEE Photonics Summer Topicals Meeting Series (SUM), Sicily, Italy, July 17-19, 2023. [PDF]
  • Jiaqi Yang, Hao Zheng, and Ahmed Louri, "Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications," in Proceedings of the Design Automation Conference (DAC), San Francisco, July 9-13, 2023. [PDF]
  • Yingnan Zhao, Ke Wang, and Ahmed Louri, “FSA: An Efficient Fault-Tolerant Systolic Array Based DNN Accelerator,” in Proceedings of the 40th IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, October 23-26, 2022. [PDF]
  • Yuechen Chen, Ahmed Louri, Shanshan Liu, and Fabrizio Lombardi, “Approximate Network-on-Chips with Application to Image Classification,” in Proceeding of the 16th International Conference on Networking, Architecture, and Storage (NAS), Philadelphia, PA, October 3-4, 2022. [PDF]
  • Jiaqi Yang, Hao Zheng, and Ahmed Louri, "Adapt-Flow: A Flexible DNN Accelerator Design for Heterogeneous Dataflow," in Proceedings of 32nd ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), Irvine, CA, June 6-8, 2022. [PDF]
  • Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, and Ahmed Louri, “AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems,” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 849-854, March 14 - 23, 2022. [PDF]
  • Yuan Li, Ahmed Louri, and Avinash Karanth, "SPACX: Silicon Photonic-based Scalable Chiplet Accelerator for DNN Inference," in Proceedings of 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 831-845, April. 2 - 6, 2022. [PDF]
  • Yuan Li, Ahmed Louri, and Avinash Karanth, "Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects," in Proceedings of 58th Design Automation Conference (DAC), San Francisco, pp. 931-936, December 5-9, 2021. [PDF]
  • Kyle Shiflett, Avinash Karanth, Ahmed Louri, and Razvan Bunescu, “Bitwise Neural Network Acceleration Using Silicon Photonics”, in Proceedings of 31st ACM Great Lakes symposium on VLSI (GLSVLSI), June 22-25, 2021. [PDF]
  • Kyle Shiflett, Avinash Karanth, Ahmed Louri and Razvan Bunescu, “Albireo: Photonic Accelerator for Deep Neural Networks,” in 48th IEEE International Symposium on Computer Architecture (ISCA-48), Valencia, Spain May 22-26, 2021. [PDF]
  • Jiajun Li, Ahmed Louri, Avinash Karanth, and  Razvan C. Bunescu, "CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters", in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA'21), Seoul, South Korea, Feb. 27 - Mar. 3, 2021. [PDF]
  • Jiajun Li, Ahmed Louri, Avinash Karanth, and Razvan C. Bunescu, "GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks", in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA'21), Seoul, South Korea, Feb. 27 - Mar. 3, 2021. [PDF]
  • Hao Zheng, Ke Wang, and Ahmed Louri, "Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architecture", in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA'21), Seoul, South Korea, Feb. 27 - Mar. 3, 2021. [PDF]
  • T. F. Canan, Savas Kaya, Avinash Karanth, and Ahmed Louri, “4-Input NAND and Nor Gates Based on Two Ambipolar Schottky Barrier FinFETs”, in proceedings of 27th IEEE International Conference on Electronics Circuits and Systems (ICECS), November 23-25, 2020. [PDF]
  • Yuechen Chen, and Ahmed Louri, “Learning-based Quality Management for Approximate Communication in Network-on-Chips”, in proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 20-25, 2020. [PDF]
  • Quintin Fettes, Kyle Shiflett, Avinash Karanth, Razvan Bunescu and Ahmed Louri, “Hardware–based Thread Migration to Reduce On-Chip Data Movement with Reinforcement Learning,” in proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 20-25, 2020. [PDF]
  • Kyle Shiflett, Avinash Karanth, Ahmed Louri and Razvan Bunescu, “Energy-Efficient Multiply-and-Accumulate Using Silicon Photonics for Deep Neural Networks,” in proceedings of 2020 IEEE Photonics Conference (IPC), Vancouver, Canada, 27 September - 1 October, 2020. [PDF]
  • Hao Zheng, Ke Wang, and Ahmed Louri, “A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures,” in proceedings of 57th Design Automation Conference (DAC’20), July 19-23, 2020. [PDF]
  • Mark Clark, Yingping Chen, Avinash Karanth, Brian Ma, and Ahmed Louri, "DoZZNoC: Reducing Static and Dynamic Energy in NoCs with Low-Latency Voltage Regulators using Machine Learning", in Proceedings of the 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS), New Orleans, LA, May 18-22, 2020. [PDF]
  • Kyle Shiflett , Dylan Wright,  Avinash Karanth , and  Ahmed Louri, "PIXEL: Photonic Neural Network Accelerator", in Proceedings of the 26th IEEE International Symposium on High-Performance Computer Architecture (HPCA'20), San Diego, CA, February 22-26, 2020. [PDF]
  • Y. Chen and A. Louri, "An Online Quality Management Framework for Approximate Communication in Network-on-Chips", in Proceedings of the 33rd International Conference on Supercomputing (ICS), Phoenix, AZ, June 26-28, 2019. [PDF]
  • K. Wang, A. Louri, A. Karanth and R. Bunescu, “IntelliNoC: A Holistic Design Framework for Energy-Efficient and Reliable On-chip Communication for Manycores”, in Proceedings of the 46th International Symposium on Computer Architecture (ISCA-46), Phoenix, Arizona, June 22-26, 2019. [PDF]
  • H. Zheng and A. Louri, “An Energy-Efficient Network-on-Chip Design using Reinforcement Learning”, in Proceedings of 56th Design Automation Conference (DAC’19), Las Vegas, NV, June 2-6, 2019. [PDF]
  • K. Wang, A. Louri, A. Karanth, and R. Bunescu, "High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learning", in Proceedings of the Design Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, March 25-29, 2019. [PDF]
  • T. F. Canan, S. Kaya, A. Karanth, H. Xin, and A. Louri, “10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs,” in Proceedings of the 25th International Conference on Electronic Circuits and Systems (ICECS), Bordeux, France, December 9-12, 2018. [PDF]
  • Y. Chen, M.F. Reza and A. Louri, “DEC-NoC: An Approximate Framework based on Dynamic Error Control with Applications to Energy-efficient NoCs,” in Proceedings of the 36th IEEE International Conference on Computer Design (ICCD), Orlando, FL, October 7-10, 2018. [PDF]
  • Y. Kelestemur, S. Laha, S. Kaya, A. Karanth, H. Xin, and A. Louri, “Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs,” in Proceedings of the 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) , Windsor, Canada, August, 5-8, 2018. [PDF]
  • M. Clark, A. Kodi, R. Bunescu and A. Louri, “LEAD: Learning-enabled Energy-Aware Dynamic Voltage/Frequency Scaling in NoCs,” in Proceedings of the 55th Design Automation Conference (DAC), San Francisco, CA, June 24-28, 2018. [PDF]
  • A. Kodi, K. Shiflett, S. Kaya, S. Laha and A. Louri, “Power-Efficient Kilo-Core Photonic-Wireless Hybrid NoCs,” in Proceedings of the 32nd IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Vancouver, BC, May 21-25, 2018. [PDF]
  • S. V. Winkle, A. Kodi, R. Bunescu and A. Louri, “Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning,” in Proceedings of the 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Vienna, February 24-28, 2018. [PDF]
  • Y. Sharma, J. Wu, A. Kantemur, J. Tak, A. Kodi, S. Kaya, A. Louri and H. Xin, “Reconfigurable Intra-chip Antenna for Future Wireless Communications,” in Proceedings of the 2018 USNC-USRI National Radio Science Meeting, Boulder, CO, January 4-8, 2018. [Link]
  • P. Roychowdhury and A. Louri, “Reconfigurable All-Photonic Inter-Rack Interconnect for Data-Centers,” in Proceedings of Frontiers in Optics 2017, Washington, D.C., September 18-21, 2017. [Link]
  • T. F. Canan, S. Kaya, A. Kodi, H. Xin and A. Louri, “Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs,” in Proceedings of the 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, August 6-9, 2017, pp. 100-103. [PDF]
  • Y. Kelestemur, S. Laha, S. Kaya, A. Kodi, H. Xin and A. Louri, “mm-Wave tunable colpitts oscillators based on FinFETs,” in Proceedings of the 2017 IEEE 18th Wireless and Microwave Technology Conference (WAMICON), Cocoa Beach, FL, April 24-25, 2017, pp. 1-6. [PDF]
  • D. DiTomaso, A. Sikder, A. Kodi and A. Louri, “Machine learning enabled power-aware Network-on-Chip design,” in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, March 27-31, 2017, pp. 1354-1359. [PDF]
  • D. DiTomaso, T. Boraten, A. Kodi and A. Louri, "Dynamic error mitigation in NoCs using intelligent prediction techniques," in Proceedings of the 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Taipei, October 15-19, 2016, pp. 1-12.
  • Ashif I. Sikder, Avinash K. Kodi, and Ahmed Louri. "Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing." In Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication (NANOCOM ‘16). ACM, New York, NY, September 28-30, 2016, Article 25, 6 pages. [PDF]
  • T. J. Kao and A.and Louri, “Design of high bandwidth photonic NoC architectures using optical multilevel signaling” in Proceedings of the 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Nara, August 31 - September 2, 2016, pp. 1-4. [PDF]
  • M. A. I. Sikder, A. K. Kodi, M. Kennedy, S. Kaya and A. Louri, “OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures” in Proceedings of the Proceedings of the 2015 IEEE 23rd Annual Symposium on High-Performance Interconnects (HOTI), Santa Clara, CA, August 26-28, 2015, pp. 44-51. [PDF]
  • B. Khemka, D. Machovec, C. Blandin, H. J. Siegel, S. Hariri, A. Louri, C. Tunc,Tunc F. Fargo and A. A. Maciejewski, “Resource Management in Heterogeneous Parallel Computing Environments with Soft and Hard Deadlines,” in Proceedings of the 11th Metaheuristics International Conference (MIC 2015), Agadir, June 7-10, 2015, pp. 1-10. [PDF]
  • Stéphane Zuckerman, Haitao Wei, Guang R. Gao, Howard Wong, Jean-Luc Gaudiot, and Ahmed Louri, " A Holistic Dataflow-Inspired System Design." in Proceedings of the 2014 Fourth Workshop on Data-Flow Execution Models for Extreme Scale Computing (DFM ‘14). IEEE Computer Society, Washington, DC, USA, August 24, 2014 pp. 46-49. [PDF]
  • D. DiTomaso, A. Kodi and A. Louri, “QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers,” in Proceedings of the 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), Orlando, FL, February 15-19, 2014, pp. 320-331. [PDF]
  • P. Poluri and A. Louri, “An Improved Router Design for Reliable On-Chip Networks,” in Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, Phoenix, AZ, May 19-23, 2014, pp. 283-292. [PDF]
  • P. Poluri and A. Louri, “Tackling Permanent Faults in the Network-on-Chip Router Pipeline,” in Proceedings of the 2013 25th International Symposium on Computer Architecture and High Performance Computing, Porto de Galinhas, October 23-26, 2013, pp. 49-56. [PDF]
  • R. Morris, A. Kodi and A. Louri, “Evaluating the Scalability and Performance of 3D Stacked Reconfigurable Nanophotonic Interconnects,” in Proceedings of the 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Austin, TX, June 2, 2013, pp. 1-1. [PDF]
  • D. DistributedTomaso, R. Morris, E. Jolley, A. Sarathy, A. Louri and A. Kodi, “Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs,” in Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, Cambridge, MA, May 20-24, 2013, pp. 876-883. [PDF]
  • R. Morris, A. K. Kodi and A. Louri, “Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance,” in Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, Vancouver, BC, December 1-5, 2012, pp. 282-293. [PDF]
  • R. Morris, A. K. Kodi and A. Louri, “3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores,” in Proceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD), Montreal, QC, September 30-October 2, 2012, pp. 413-418. [PDF]
  • D. DiTomaso, T. Boraten, A. Kodi andnd A. Louri, “Evaluation of fault tolerant channel buffers for improving reliability in NoCs,” in Proceedings of the 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, August 5-8, 2012, pp. 182-185. [PDF]
  • Jacques Henri Collet, Ahmed Louri, Vivek Tulsidas Bhat, and Pavan Poluri. 2011. "ROBUST: a new self-healing fault-tolerant NoC router." In Proceedings of the 4th International Workshop on Network on Chip Architectures (NoCArc ‘11). ACM, New York, NY, December 4, 2011, pp. 11-16. [PDF]
  • A. Kodi, R. Morris, D. DiTomaso, A. Sarathy and A. Louri, “Co-design of channel buffers and crossbar organizations in NoCs architectures,” in Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 6-10, 2011, pp. 219-226. [PDF]
  • M. Jacquesnicki, J. H. Collet, A. Louri and A. Napieralski, “Hot spots and core-to-core thermal coupling in future multi-core architectures,” in Proceedings of the 2010 26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), Santa Clara, CA, February 21-25, 2010, pp. 205-210. [PDF]
  • X. Zhang and A. Louri, “A multilayer nanophotonic interconnection network for on-chip many-core communications,” in Proceedings of the Design Automation Conference, Anaheim, CA, June 13-18, 2010, pp. 156-161. [PDF]
  • J. Sun, Roman Lysecky, Karthik Shankar, A. Kodi, A. Louri and J. M. Wang, “Workload capacity considering NBTI degradation in multi-core systems,” in Proceedings of the 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, January 18-21, 2010, pp. 450-455. [PDF]
  • R. K. B. Raghavendra, J. M. Wang, A. K. Kodi and A. Louri, “A Robust High Speed Link Design for NoC at 65nm Technology Node,” in Proceedings of the Austin Conference on Integrated Systems & Circuits (ACISC’09), Austin, TX, October 26-27, 2009, pp. 1-6. [PDF]
  • X. Zhang and A. Louri, “Nanophotonic Interconnects and 3-D Stacked Technology for Future Many-Core Architectures,” in Proceedings of Frontiers in Optics 2009/Laser Science XXV/Fall 2009 OSA Optics & Photonics Technical Digest, San Jose, CA, October 11-26, 2009, pp. 156-161. [Link]
  • A. K. Kodi, R. Morris, A. Louri and X. Zhang, “On-Chip photonic interconnects for scalable multi-core architectures,” in Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, CA, May 10-13, 2009, pp. 90-90. [PDF]
  • A. Kodi, A. Louri and J. Wang, “Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs),” in Proceedings of the 2009 10th International Symposium on Quality Electronic Design, San Jose, CA, March 16-18, 2009, pp. 826-832. [PDF]
  • J. Sun, A. Kodi, A. Louri and J. M. Wang, “NBTI awarere workload balancing in multi-core systems,” in Proceedings of the 2009 10th International Symposium on Quality Electronic Design, San Jose, CA, March 16-18, 2009, pp. 833-838. [PDF]
  • A. K. Kodi, A. Sarathy, A. Louri and J. Wang, “Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures,” in Proceedings of the 2009 Asia and South Pacific Design Automation Conference, Yokohama, January 19-22, 2009, pp. 1-6 [PDF]
  • A. K. Kodi and A. Louri, “Efficient Dynamic Bandwidth Re-allocation in Photonic Networks using SOI-based Microring Resonators,” in Proceedings of the Frontiers in Optics 2008/Laser Science XXIV/Plasmonics and Metamaterials/Optical Fabrication and Testing, Rochester, NY, October 19-23, 2008, pp. 1-1. [Link]
  • A. K. Kodi, A. Sarathy and A. Louri, “iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures,” in Proceedings of the 2008 International Symposium on Computer Architecture, Beijing, June 21-25, 2008, pp. 241-250. [PDF]
  • Avinash Kodi, Ashwini Sarathy, Ashwinind Ahmed Louri. "Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture." In Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems (ANCS ‘07). ACM, Orlando, FL, December 3-4, 2007 pp. 47-56. [PDF]
  • A. Kodi and A. Louri, “Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems,” Supercomputing, 2007. SC ‘07. Proceedings of the 2007 ACM/IEEE Conference on, Reno, NV, November 10-16, 2007, pp. 1-12. [PDF]
  • C. Kochar, A. Kodi and A. Louri, “Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators,” in Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007), Stanford, CA, August 22-24, 2007, pp. 54-64. [PDF]
  • A. K. Kodi and A. Louri, “Power-Aware Bandwidth-Resonatorsconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems,” in Proceedings of the 2007 IEEE International Parallel and Distributed Processing Symposium, Long Beach, CA, March 26-30, 2007, pp. 1-10. [PDF]
  • A. K. Kodi and A. Louri, “A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems,” in Proceedings of the 14th IEEE Symposium on High-Performance Interconnects (HOTI ‘06), Stanford, CA, August 23-25, 2006, pp. 31-36. [PDF]
  • A. K. Kodi and A. Louri, “Switchless Photonic Architecture for Parallel Computers,” in Proceedings of Frontiers in Optics 2005, Tucson, AZ, October 16-20, 2005, pp. 1-1. [Link]
  • A. K. Kodi and A. Louri, “Scalable optical interconnection network for parallel and distributed computing,” in Proceedings of the 2005 OSA Topical Meeting on Information Photonics (IP), Charlotte, NC, June 6-9, 2005, pp. 1-3. [Link]
  • A. K. Kodi and A. Louri, “Design of a high-speed optical interconnect for scalable shared memory multiprocessors,” in Proceedings of the 12th Annual IEEE Symposium on High Performance Interconnects, Stanford, CA, August 25-27, 2004, pp. 92-97. [PDF]
  • A. K. Kodi and A. Louri, “A scalable architecture for distributed shared memory multiprocessors using optical interconnects,” in Proceedings of the 18th International Parallel and Distributed Processing Symposium, Santa Fe, NM, April 26-30, 2004, pp. 1-10. [PDF]
  • A. K. Kodi and A. Louri, “Parallel Optical Interconnection Network for SMPs,” in Proceedings of Frontiers in Optics 2003, Tucson, AZ, October 5-9, 2003, pp. 1-1. [Link]
  • A. Louri and A. K. Kodi, “Design of large-scale symmetric multiprocessors (SMPs) using parallel optical interconnects,” in Proceedings of the ACS/IEEE International Conference on Computer Systems and Applications, 2003, Tunis, Tunisia, July 14-18, 2003, pp. 11-14. [PDF]
  • A. K. Kodi and A. Louri, “Optical Interconnects for Large-Scale Symmetric Multiprocessor Networks,” in Proceedings of Optics in Computing 2002, Taipei, April, 2002, pp. 1-1.
  • P. Y. Choo and A. Louri, “A DWDM IP-Routing Lookups and Forwarding Scheme using Multiwavelength Optical Content-Addressable Memory Processing,” in Proceedings of the 6th International Conference on Computer Science and Informatics, Durham, NC, March 8-16, 2002, pp. 1-7.
  • A. K. Kodi and A. Louri, “Y-junction based addressing in optical symmetric multiprocessor networks,” in Proceedings of the 14th Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS ‘01), San Diego, CA, November 11-15, 2001, pp. 865-866. [PDF]
  • R. Ivey and A. Louri, “Optical crossbar based interconnection network for scalable symmetric multiprocessors,” in Proceedings of Optics in Computing 2001, Lake Tahoe, NV, January 9-11, 2001, pp. 90-94. [Link]
  • P. Choo and A. Louri, “Guided-wave multiwavelength Content-Addressable Memory (CAM) processing module for database and networking applications,” in Proceedings of Optics in Computing 2001, Lake Tahoe, NV, October 22-26, 2001, pp. 1-7. [Link]
  • R. Ivey and A. Louri, “Crossbarsbar-Connected Optical Interconnects using VCSEL Arrays,” in Proceedings of Optics for the New Millenium, Providence, RI, October 22-26, 2000, pp. 1-7.
  • P. Choo and A. Louri, “Guided-Wave Multiwavelength Computing Systems,” in Proceedings of Optics for the New Millenium, Providence, RI, 2000, pp. 1-7.
  • A. Detofsky, P. Y. Choo andd A. Louri, “The Equivalency Processing Parallel Photonic Integrated Circuit (EP31C), a Parallel Digital Equivalence Search Module,” in Proceedings of the 29th Applied Imagery Pattern Recognition Workshop, Washington, D.C., October 16-18, 2000, pp. 64-70. [PDF]
  • B. Webb and A. Louri, “A Scalable All-Optical Crossbar Network Using Wavelength Division Multiplexing and Tunable Verical-Cavity Surface Emitting Lasers,” in Proceedings of the 1999 IEEE 7th Annual Symposium on High-Performance Interconnects (HOTI), Stanford, CA, August 18-20, 1999, pp. 1-7.
  • P. Y. Choo, A. Detofsky, and A. Louri, “A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental System,” in Proceedings of Optics in Computing 1999, Snowmass, CO, April 12-16, 1999, pp. 66-69. [Link]
  • P. Y. Choo, A. Detofsky, and A. Louri, “A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental Results,” in Proceedings of the Workshop on Optics in Computer Science (WOCS ‘99), San Juan, PR, April 14-16, 1999, pp. 873-886.
  • T. S. Jones and A. Louri, “Media Access Protocols for a Scalable Optical Interconnection Network,” in Proceedings of the 1998 International Conference on Parallel Processing, Minneapolis, MN, August 15-20, 1998, pp. 1-8.
  • T. S. Jones and A. Louri, “Channel allocation, power budget and bit error rate in hierarchical optical ring interconnection network (HORN),” in Proceedings of the 5th International Conference on Massively Parallel Processing, Las Vegas, NV, June 14-16, 1998, pp. 123-130.
  • B. Webb and A. Louri, “A free space optical crossbar switch using wavelength division multiplexing and vertical-cavity surface-emitting lasers,” in Proceedings of the 5th International Conference on Massively Parallel Processing, Las Vegas, NV, June 14-16, 1998, pp. 50-57.
  • P. Y. Choo, A. Detofsky, and A. Louri, “An Optical Architecture Using Multiwavelength and Polarization Encoding for High-Speed Parallel Relational Database Processing,” in Proceedings of the Optics in Computing 1998, Bruges, June 17-20, 1998, pp. 139-143.
  • A. Louri and R. Gupta, “Hierarchical optical ring interconnectiontion (HORN): a scalable interconnection-network for multiprocessors and massively parallel systems,” in Proceedings of the 1996 3rd International Conference on Massively Parallel Processing Using Optical Interconnections, Maui, HI, October 27-29, 1996, pp. 247-254.
  • A. Louri and H. K. Sung, “An efficient 3D optical Implementationion of binary de Bruijn networks with applications to massively parallel computing,” in Proceedings of the 1995 2nd International Conference on Massively Parallel Processing Using Optical Interconnections, San Antonio, TX, October 23-24, 1995, pp. 152-159.
  • A. Louri, J. A. Hatch, and J. Na, “Constant-time parallel sorting algorithm and its optical implementation using smart pixels,” in Proceedings of the 1995 Annual Topical Meeting on Optical Computing, Salt Lake City, UT, March 12-17, 1995, pp. 1-6.
  • A. Louri, H. K. Sung, Y. Moon, and B. Zeigler, “An Efficient Signal Distinction Scheme for Large-scale Free-space Optical Networks Using Genetic Algorithms,” in Proceedings of the 1995 Annual Topical Meeting on Photonics in Switching, Salt Lake City, UT, March 12-17, 1995, pp. 90-92.
  • A. Louri and H. K. Sung, “Free-Space Optical Implementation of DeBruijn Networks,” in Proceedings of the 1994 Annual Meeting of the Optical Society of America, Dallas, TX, October 2-7, 1994, pp. 1-6.
  • A. Louri and H. K. Sung, “A Scalable Optical Interconnection Network for Massively Parallel Computers,” in Proceedings of the 1994 International Conference on Optical Computing, Edinburgh, August 22-25, 1994, pp. 223-224.
  • A. Louri and J. A. Hatch, “The Physical Design of an Opticalcal Content-Addressable Parallel Processor,” in Proceedings of the 1994 International Conference on Optical Computing, Edinburgh, August 22-25, 1994, pp. 89-90.
  • A. Louri and J. A. Hatchh, “An Optical Content-Addressable Parallel Processor for High-Speed Database Processing,” in Proceedings of the 1994 International Conference on Frontiers in Information Optics, Kyoto, April 4-8, 1994, pp. 1-11.
  • A. Louri and H. K. Sung, “A hypercube-based optical interconnection network: a solution to the scalability requirements for massively parallel computers,” in Proceedings of the 1st International Workshop on Massively Parallel Processing Using Optical Interconnections, Cancun, April 26-27, 1994, pp. 81-93.
  • E. Hokens and Addressable. Louri, “Performance Considerations Relating to the Design of Interconnection Networks for Multiprocessors Systems,” in Proceedings of the 1993 International Conference on Parallel Processing (ICPP ‘93), Syracuse, NY, August 16-20, 1993, pp. 206-209.
  • A. Louri and J. A. Hatch, “High-Speed Database Processing on an Optical Content-Addressable Parallel Processor (OCAPP),” in Proceedings of the 1993 International Topical Meeting on Optical Computing, Palm Springs, CA, March 16-19, 1993, pp. 50-52.
  • A. Louri and H. K. Sung, “Efficient Implementationentation methodology for three-dimensional space-invariant hypercube-based optical interconnection networks,” in Proceedings of the 1993 International Topical Meeting on Photonics in Switching, Palm Springs, CA, March 15-17, 1993, pp. 1-10.
  • A. Louri, “An Algorithm for Implementing Fully-Connected Optical Interconnectionn Networks with Broadcast Capability,” in Proceedings of the 1993 International Topical Meeting on Optical Computing, Palm Springs, CA, March 16-19, 1993, pp. 168-169.
  • A. Louri And H. K. Sung, “A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation,” in Proceedings of the 1992 International Conference on Parallel Processing, St. Charles, IL, August 17-21, 1992, pp. 1-7.
  • A. Louri and H. K. Sung,Sung “A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation,” in Proceedings of the 1992 19th Annual International Symposium on Computer Architecture, Gold Coast, Queensland, May 19-23, 1992, pp. 428-428.
  • A. Louri and J. Na, “Parallel Electro-Optical Rule-Based System for Fast Execution of Expert Systems,” in Proceedings of the 19th Annual International Symposium on Computer Architecture, Gold Coast, Queensland, May 19-23, 1992, pp. 427-427.
  • A. Louri and J. Na, “Parallel electro-optical rule-based Symposiumystem for fast execution of expert systems,” in Proceedings of the 25th Hawaii International Conference on System Sciences, Kauai, HI, January, 1992, pp. 369-380.
  • N. J.1991 Lee and A. Louri, “Microcanonical mean field annealing: a new algorithm for increasing the convergence speed of mean field annealing,” in Proceedings of the 1991 Internation Joint Conference on Neural Networks, Singapore, November, 1991, pp. 941-946.
  • S. Y. Kuo, A. Louri and S. C. Liang, “Design and Evaluation of Fastault-Tolerant Interleaved Memory Systems,” in Proceedings of the 1991 20th Annual International Conference on Parallel Processing, Chicago, IL, August, 1991, pp. 1-8.
  • A. Louri, “An Optical Content-Addressable Parallel Processor for Fast Searching and Retrieving,” in Proceedings of the Parallel Architectures and Languages Europe (PARLE ‘91), Eindhoven, June, 1991, pp. 338-354.
  • A. Louri, “Design of an optical content-addressable parallel processor with applications to fast searching and information retrieval,” in Proceedings of the 5th International Parallel Processing Symposium, Anaheim, CA, April, 1991, pp. 234-239.
  • A. Louri, "Roles of Optics in High-Performance Computing Systems," in Proceedings of the 1st Workshop on Architecture for Free Space Digital Optical Computing and Networking, Vail, CO, January, 1991, pp. 1-8.
  • Architecture. Louri and A. Post, “Optimal Implementation of Arbitrary Boolean Functions using Space-Variant Optics,” in Proceedings of OPTCON ‘90, Boston, MA, November, 1990, pp. 1-8.
  • A. Louri, “Parallel Implementation of Multi-Rule Optical Symbolic Substitution Processors Using Wavelength Multiplexing,” in Proceedings of the 1990 International Topical Meeting on Optical Computing, Kobe, April, 1990, pp. 63-66.
  • A. Louri, “Impact of Data Encoding Schemes on the Throughput of Optical Symbolic Substitution Systems,” in Proceedings of the 1990 International Topical Meeting on Optical Computing, Kobe, April, 1990, pp. 1-8.
  • A. Louri, “Symbolic Substitution-Based Optical Architectures and Algorithms for High-Speed Parallel Processing,” in Proceedings of the 1990 18th Annual Computer Science Conference, Washington, D.C., February, 1990, pp. 173-179.
  • A. Louri, “A preliminary version of an optical data-flow architecture,” in Proceedings of the 23rd Annual Hawaii International Conference on System Sciences, Kailua-Kona, HI, January 3-6, 1990, pp. 121-130.
  • A. Louri, “An Optical Architecture and Algorithms for Data-Parallel Computing,” in Proceedings of the 13th Annual Computer Software and Applications Conference, Orlando, FL, September 18-22, 1989, pp. 1-8.
  • A. Louri, “An Optical Data-Flow Computer,” in Proceedings of the 33rd Annual Technical Symposium on Optical Information Processing Systems and Architectures, San Diego, CA, August 6-11, 1989, pp. 1-12.
  • A. Louri, “Architectures Massively Parallel Optical Computer,” in Proceedings of the 1989 Annual Topical Meeting on Optical Computing, Salt Lake City, UT, February, 1989, pp. 96-100.
  • K. Hwang and A. Louri, “Optical arithmetic Using signed-digit symbolic substitution,” in Proceedings of the 1988 17th Annual International Conference on Parallel Processing, St. Charles, IL, August 15-19, 1988, pp. 55-64.
  • K. Hwang and A. Louri, “A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution,” in Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, HI, May 30-June 2, 1988, pp. 18-27.
  • K. Hwang and A. Louri, “New Symbolic Substitution Algorithms for Optical Arithmetic using Signed-Digit Representation,” in Proceedings of the Society of Photographic Instrumentation Engineers - International Society for Optical Engineering, Los Angeles, CA, January, 1988, pp. 90-99.
  • K. Hwang and A. Louri, "Parallel Architecturees for Optical Computing," in Proceedings of the 3rd International SIAM Conference on Parallel Processing and Scientific Computing, Los Angeles, CA, December 1-4, 1987, pp. 414-428.
  • K. Hwang and A. Louri, “Ultrafast Optical Arithmetic Architectures with Symbolc Substitution,” in Proceedings of the 1987 Annual Optical Society of America Meeting (Optics ‘87), Rochester, NY, October 18-23, 1987, pp. 126-127.
  • K. Hwang, Z. Xu and A. Louri, “Remps, An Electro-Optical Supercomputer for Parallel Solution of PDE Problems,” in Proceedings of the 1987 2nd Annual International Conference on Supercomputing, Santa Clara, CA, May 5-8, 1987, pp. 301-311.
Mobirise
HPCAT Lab
High Performance Computing Architectures & Technologies Lab

Department of Electrical and Computer Enginnering
School of Engineering and Applied Science
The George Washington University

800 22nd Street NW
Washington, DC 20052
United States of America 

Contact

Ahmed Louri, IEEE Fellow
David and Marilyn Karlgaard Endowed Chair Professor of ECE
Director,  HPCAT Lab 


Email: louri@gwu.edu                    
Phone: +1 (202) 994 8241

© Copyright 2019 HPCAT - All Rights Reserved

Made with Mobirise site theme